1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device to which an SOI substrate is applied.
2. Description of the Background Art
In an inverter circuit for operating a load such as induction motor, a lateral insulated gate bipolar transistor (LIGBT), for example, is applied as a switching device. In this type of semiconductor device, an SOI (Silicon On Insulator) substrate is applied as a substrate on which an n-channel LIGBT is formed. In the SOI substrate, an N− semiconductor layer is formed on a main surface of a semiconductor substrate with an insulating film interposed therebetween.
In the N− semiconductor layer, a first P-type impurity region is formed from the surface of the N− semiconductor layer to a predetermined depth. A first N-type impurity region is formed to surround the first P-type impurity region laterally and from below. A collector electrode is formed to contact the surface of the first P-type impurity region. In a portion located directly below the collector electrode and between the N− semiconductor layer and the semiconductor substrate, a hollow region is formed.
In a predetermined region of the N− semiconductor layer that is spaced from the first N-type impurity region, a second N-type impurity region is formed from the surface of the N− semiconductor layer to a predetermined depth. A second P-type impurity region is formed to surround the second N-type impurity region laterally and from below. On the surface of a portion of the second P-type impurity region that is located between the second N-type impurity region and the N− semiconductor layer, a gate electrode is formed with a gate insulating film interposed therebetween. An emitter electrode is formed to contact the surface of the second P-type impurity region and the surface of the second N-type impurity region. The emitter electrode, the collector electrode, and the gate electrode constitute respective electrodes of the LIGBT.
When the semiconductor device is OFF state, a depletion layer expands from the interface between the second P-type impurity region and the N− semiconductor layer chiefly toward the N− semiconductor layer. At this time, the impurity concentration and the thickness of the N− semiconductor layer can be adjusted to entirely deplete the N− semiconductor layer and, under the condition that the electric field at the surface of the N− semiconductor layer is substantially uniform, a maximum breakdown voltage is obtained.
Under this condition, if the distance (spacing) between the emitter (electrode) and the collector (electrode) is increased, finally the breakdown voltage of the whole semiconductor device is restricted due to electric field concentration on a portion of the N− semiconductor layer that is located directly below the collector (electrode). Although extension of the first N-type impurity region and the collector electrode toward the location of the emitter electrode is unnecessary for the basic operation of the IGBT, it has an effect of restricting expansion of the depletion layer in the vicinity of the surface of the N− semiconductor layer in the OFF state.
The structure in which the hollow region is formed between the N− semiconductor layer and the semiconductor substrate is a structure with the purpose of increasing the breakdown voltage, and is proposed for example in PTL 1 (Japanese Patent No. 2739018), PTL 2 (Japanese Patent Laying-Open No. 2006-148017), and PTL 3 (Japanese Patent Laying-Open No. 2006-173204). In a laminate structure made up of a semiconductor substrate (silicon), an insulating film (silicon oxide film), and a hollow region, the field intensity ratio corresponds to the reciprocal of the dielectric constant ratio. Here, since the dielectric constant ratio between the N− semiconductor layer (silicon), the insulating film (silicon oxide film), and the hollow region is about 12:4:1, the voltage drop across the hollow region can be set large and accordingly the voltage drop across the N− semiconductor layer can be made small. In this way, the electric field in the N− semiconductor layer can be alleviated to restrict expansion of the depletion layer, and consequently the breakdown voltage of the semiconductor device can be improved.